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| 4-BIT SERIAL-to-PARALLEL CONVERTER SY10E445 SY100E445 FEATURES s On-chip clock DESCRIPTION /4 and /8 The SY10/100E445 are integrated 4-bit serial-to-parallel data converters. The devices are designed to operate for NRZ data rates of up to 2.5Gb/s. The chip generates a divide-by-4 and a divide-by-8 clock for both 4-bit conversion and a two-chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1, etc. Two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the E446 parallel-to-serial converter. The start bit for conversion can be moved using the SYNC input. A single pulse, applied asynchronously for at least two input clock cycles, shifts the start bit for conversion from Qn to Qn-1 by one bit. For each additional shift required, an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to "swallow" a clock pulse, effectively shifting a bit from the Qn to the Qn-1 output (see Timing Diagram B). The MODE input is used to select the conversion mode of the device. With the MODE input LOW (or open) the device will function as a 4-bit converter. When the mode input is driven HIGH, the data on the output will change on every eighth clock cycle, thus allowing for an 8-bit conversion scheme using two E445s. When cascaded in an 8-bit conversion scheme, the devices will not operate at the 2.5Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445. For lower data rate applications, a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500MHz, differential input signals are recommended. For single-ended inputs, the VBB pin is tied to the inverting differential input and bypassed via a 0.01F capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal. s Extended 100E VEE range of -4.2V to -5.5V s 2.5Gb/s data rate capability s Differential clock and serial inputs s VBB output for single-ended use s Asynchronous data synchronization s Mode select to expand to 8 bits s Internal 75k input pull-down resistors s Fully compatible with Motorola MC10E/100E445 s Available in 28-pin PLCC package PIN CONFIGURATION RESET SINA SINA SYNC MODE NC VCCO 25 24 23 22 21 20 19 SINB SINB SEL VEE CLK CLK VBB 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 SOUT SOUT VCC Q0 Q1 VCCO Q2 TOP VIEW PLCC J28-1 16 15 14 13 12 VCCO CL/4 PIN NAMES Pin SINA, SINA SINB, SINB SEL SOUT, SOUT Q0-Q3 CLK, CLK CL/4, CL/4 CL/8, CL/8 MODE SYNC RESET VCCO Function Differential Serial Data Input A Differential Serial Data Input B Serial Input Select Pin Differential Serial Data Output Parallel Data Outputs Differential Clock Inputs Differential /4 Clock Output Differential /8 Clock Output Conversion Mode 4-bit/8-bit Conversion Synchronizing Input Input, Resets the Counters VCC to Output VCCO Q3 CL/8 CL/8 CL/4 Rev.: D Amendment: /0 1 Issue Date: October, 1998 Micrel SY10E445 SY100E445 BLOCK DIAGRAM SINB SINB SINA SINA SEL D Q D Q 0 1 D D Q D Q Q3 Q2 D Q D Q Q1 D Q D Q Q0 SOUT SOUT CLK CLK /4 R 0 /2 R MODE RESET SYNC VBB 1 CL/8 CL/8 CL/4 CL/4 2 Micrel SY10E445 SY100E445 TRUTH TABLES LOGIC DIAGRAM Mode L H Conversion 4-Bit 8-Bit SEL H L Serial Input A B DC CHARACTERISTICS LOGIC DIAGRAM VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH VOH Parameter Input HIGH Current Output HIGH Voltage (SOUT only) 10E (SOUT only) 100E Output Reference Voltage 10E 100E Power Supply Current 10E 100E -- -- 154 154 185 185 -- -- 154 154 185 185 -- -- 154 177 185 212 Min. -- -1020 -1025 -1.38 -1.38 Typ. -- -- -- -- -- Max. 150 TA = +25C Min. -- Typ. -- -- -- -- -- Max. 150 -- TA = +85C Min. Typ. -- -- -- -- -- Max. 150 -670 -830 V -1.27 -1.35 -1.26 -1.38 -1.25 -1.31 -1.26 -1.38 -1.19 -1.26 mA -- Unit A V -790 -980 -830 -1025 -760 -910 -830 -1025 1 1 Condition -- VBB IEE NOTE: 1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E and 100E VOH levels. AC CHARACTERISTICS LOGIC DIAGRAM VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fMAX tPLH tPHL Parameter Max. Conversion Frequency Propagation Delay to Output CLK to Q CLK to SOUT CLK to CL/4 CLK to CL/8 Set-up Time SINA, SINB SEL Hold Time, SINA, SINB, SEL Reset Recovery Time Minimum Pulse Width CLK, MR Rise/Fall Times 20% to 80% SOUT Other Min. 2.0 2.5 1500 800 1100 1100 -100 0 450 500 400 Typ. -- -- 1800 975 1325 1325 -250 -200 300 300 -- Max. -- -- 2100 1150 1550 1550 -- -- -- -- -- 2.0 2.5 1500 800 1100 1100 -100 0 450 500 400 TA = +25C Min. Typ. -- -- 1800 975 1325 1325 -250 -200 300 300 -- Max. -- -- 2100 1150 1550 1550 -- -- -- -- -- 2.0 2.5 1500 800 1100 1100 -100 0 450 500 400 TA = +85C Min. Typ. -- -- 1800 975 1325 1325 -250 -200 300 300 -- Max. -- -- 2100 1150 1550 1550 ps -- -- -- -- -- ps ps ps ps 100 200 225 425 350 650 100 200 225 425 350 650 100 200 225 425 350 550 -- -- -- -- -- Unit Gb/s NRZ ps Condition 1 2 -- tS tH tRR tPW tr tf NOTES: 1. Guaranteed for input clock amplitudes of 150mV to 800mV. 2. Guaranteed for input clock amplitudes of 150mV to 400mV. 3 Micrel SY10E445 SY100E445 APPLICATIONS INFORMATION LOGIC DIAGRAM The SY10/100E are integrated 1:4 serial-to-parallel converters. The chips are designed to work with the E446 devices to provide both transmission and receiving of a high-speed serial data path. The E445, under special input conditions, can convert up to a 2.5Gb/s NRZ data stream into 4-bit parallel data. The device also provides a divide-by-four clock output to be used to synchronize the parallel data with the rest of the system. The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 1 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E445 has an extra buffer delay and, thus, should be used as the loop back serial input. SOUT SOUT To Serial Medium Clock Clock E445a Serial Input Data SIN SIN SOUT SOUT SIN SIN Q3 Q2 Q1 Q0 E445b Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Parallel Output Data 100ps Clock Tpd CLK to SOUT 800ps 1050ps Parallel Data Figure 2. Cascaded 1:8 Converter Architecture Parallel Data SINA SINA SINB SINB From Serial Medium Figure 1. Loop Test Architecture clock-to-serial-out would potentially cause a serial bit to be swallowed (Figure 3). With a minimum delay of 800ps on this output, the clock for the lower order E445 cannot be delayed more than 800ps relative to the clock of the first E445 without potentially missing a bit of information. Because the set-up time on the serial input pin is negative, coincident excursions on the data and clock inputs of the E445 will result in correct operation. Clock a The E445 features a differential serial output and a divide-by-8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 2 illustrates the architecture of a 1:8 demultiplexer using two E445s. The timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the higher order device. This feedthrough of the serial inputs bounds the upper end of the frequency of operation. The clock-to-serial output propagation delay, plus the set-up time of the serial input pins, must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, tPD CLK to SOUT = 1150ps or a clock frequency of 950MHz. The clock frequency is significantly lower than that of a single converter. To increase this frequency, some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445, the frequency of operation can be increased. The delay between the two clocks can be increased until the minimum delay of 4 Clock b Tpd CLK to SOUT 800ps 1050ps Figure 3. Cascade Frequency Limitation Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs of the E445. By connecting the clock for the second E445 to the complimentary clock input pin, the device will clock a half a clock period after the first E445 (Figure 4). Utilizing this simple technique will raise the potential conversion frequency up to 1.5GHz. The divideby-eight clock of the second E445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two E445s will no longer be synchronized. This skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses. Micrel SY10E445 SY100E445 TIMING DIAGRAM LOGIC DIAGRAMS CLK SIN RESET Q0 Q1 Q2 Q3 SOUT CL/8 CL/4 Dn-4 Dn-4 Dn-3 Dn-2 Dn-1 Dn-3 Dn-2 Dn-1 Dn Dn Dn+1 Dn+2 Dn+3 Dn+1 Dn+2 Dn+3 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Timing Diagram A. 1:4 Serial to Parallel Conversion CLK SIN RESET SYNC Q0 Q1 Q2 Q3 SOUT CL/4 CL/8 Dn-4 Dn-3 Dn-4 Dn-3 Dn-2 Dn-1 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+1 Dn+2 Dn+3 Dn+4 Dn+3 Dn+4 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 Timing Diagram B. 1:4 Serial to Parallel Conversion with SYNC Pulse 5 Micrel Clock Clock E445a Serial Input Data SIN SIN SOUT SOUT SIN SIN Q3 Q2 Q1 Q0 E445b SY10E445 SY100E445 667ps (1.5GHz) Clock a Clock b Tpd CLK to SOUT 800ps 1050ps Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 100ps Q3 Q2 Q1 Q0 Parallel Output Data Figure 4. Extended Frequency 1:8 Demultiplexer CLK SINa Q0 Q1 Q2 Q3 Q4 (Q0 a) Q5 (Q1 a) Q6 (Q2 a) Q7 (Q3 a) SOUTa SOUTb CL/4a CL/4b CL/8a CL/8b Dn-4 Dn-3 Dn-2 Dn-1 Dn-4 Dn Dn-3 Dn+1 Dn-2 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+2 Dn-1 Dn+3 Dn Dn+1 Timing Diagram PRODUCT ORDERING CODE Ordering Code SY10E445JC SY10E445JCTR SY100E445JC SY100E445JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 6 Micrel SY10E445 SY100E445 28 LEAD PLCC (J28-1) Rev. 03 7 Micrel SY10E445 SY100E445 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 8 |
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